bench_std_vec_from_exact_array_and_drop_exact Instructions: 166 L1 Accesses: 239 L2 Accesses: 2 RAM Accesses: 4 Estimated Cycles: 389 bench_smallvec_from_exact_array_and_drop_exact Instructions: 8 L1 Accesses: 11 L2 Accesses: 2 RAM Accesses: 3 Estimated Cycles: 126 bench_wordvec_from_exact_array_and_drop_exact Instructions: 8 L1 Accesses: 11 L2 Accesses: 2 RAM Accesses: 3 Estimated Cycles: 126 bench_thinvec_from_exact_array_and_drop_exact Instructions: 259 L1 Accesses: 365 L2 Accesses: 2 RAM Accesses: 16 Estimated Cycles: 935 bench_std_vec_from_array_and_drop_large Instructions: 169 L1 Accesses: 242 L2 Accesses: 2 RAM Accesses: 4 Estimated Cycles: 392 bench_smallvec_from_array_and_drop_large Instructions: 5 L1 Accesses: 6 L2 Accesses: 2 RAM Accesses: 3 Estimated Cycles: 121 bench_wordvec_from_array_and_drop_large Instructions: 312 L1 Accesses: 419 L2 Accesses: 2 RAM Accesses: 5 Estimated Cycles: 604 bench_thinvec_from_array_and_drop_large Instructions: 452 L1 Accesses: 618 L2 Accesses: 2 RAM Accesses: 23 Estimated Cycles: 1433 bench_std_vec_from_array_and_drop_huge Instructions: 410 L1 Accesses: 552 L2 Accesses: 2 RAM Accesses: 18 Estimated Cycles: 1192 bench_smallvec_from_array_and_drop_huge Instructions: 5 L1 Accesses: 6 L2 Accesses: 2 RAM Accesses: 3 Estimated Cycles: 121 bench_wordvec_from_array_and_drop_huge Instructions: 419 L1 Accesses: 560 L2 Accesses: 2 RAM Accesses: 17 Estimated Cycles: 1165 bench_thinvec_from_array_and_drop_huge Instructions: 9878 L1 Accesses: 14219 L2 Accesses: 23 RAM Accesses: 80 Estimated Cycles: 17134 bench_std_vec_from_iter_and_drop_empty Instructions: 19 L1 Accesses: 23 L2 Accesses: 2 RAM Accesses: 2 Estimated Cycles: 103 bench_smallvec_from_iter_and_drop_empty Instructions: 19 L1 Accesses: 23 L2 Accesses: 2 RAM Accesses: 2 Estimated Cycles: 103 bench_wordvec_from_iter_and_drop_empty Instructions: 19 L1 Accesses: 23 L2 Accesses: 2 RAM Accesses: 2 Estimated Cycles: 103 bench_thinvec_from_iter_and_drop_empty Instructions: 19 L1 Accesses: 23 L2 Accesses: 2 RAM Accesses: 2 Estimated Cycles: 103 bench_std_vec_from_iter_and_drop_small Instructions: 177 L1 Accesses: 251 L2 Accesses: 2 RAM Accesses: 3 Estimated Cycles: 366 bench_smallvec_from_iter_and_drop_small Instructions: 113 L1 Accesses: 134 L2 Accesses: 2 RAM Accesses: 10 Estimated Cycles: 494 bench_wordvec_from_iter_and_drop_small Instructions: 72 L1 Accesses: 94 L2 Accesses: 2 RAM Accesses: 6 Estimated Cycles: 314 bench_thinvec_from_iter_and_drop_small Instructions: 270 L1 Accesses: 377 L2 Accesses: 2 RAM Accesses: 15 Estimated Cycles: 912 bench_std_vec_from_iter_and_drop_large Instructions: 180 L1 Accesses: 254 L2 Accesses: 2 RAM Accesses: 3 Estimated Cycles: 369 bench_smallvec_from_iter_and_drop_large Instructions: 450 L1 Accesses: 573 L2 Accesses: 3 RAM Accesses: 19 Estimated Cycles: 1253 bench_wordvec_from_iter_and_drop_large Instructions: 475 L1 Accesses: 611 L2 Accesses: 2 RAM Accesses: 11 Estimated Cycles: 1006 bench_thinvec_from_iter_and_drop_large Instructions: 480 L1 Accesses: 651 L2 Accesses: 2 RAM Accesses: 23 Estimated Cycles: 1466 bench_std_vec_from_iter_and_drop_huge Instructions: 850 L1 Accesses: 1085 L2 Accesses: 5 RAM Accesses: 61 Estimated Cycles: 3245 bench_smallvec_from_iter_and_drop_huge Instructions: 1139 L1 Accesses: 1410 L2 Accesses: 6 RAM Accesses: 71 Estimated Cycles: 3925 bench_wordvec_from_iter_and_drop_huge Instructions: 1028 L1 Accesses: 1278 L2 Accesses: 5 RAM Accesses: 61 Estimated Cycles: 3438 bench_thinvec_from_iter_and_drop_huge Instructions: 9745 L1 Accesses: 12964 L2 Accesses: 4 RAM Accesses: 60 Estimated Cycles: 15084 bench_std_vec_from_iter_and_drop_huge_dyn Instructions: 18118 L1 Accesses: 26545 L2 Accesses: 6 RAM Accesses: 58 Estimated Cycles: 28605 bench_smallvec_from_iter_and_drop_huge_dyn Instructions: 16164 L1 Accesses: 22559 L2 Accesses: 7 RAM Accesses: 70 Estimated Cycles: 25044 bench_wordvec_from_iter_and_drop_huge_dyn Instructions: 18147 L1 Accesses: 25558 L2 Accesses: 5 RAM Accesses: 66 Estimated Cycles: 27893 bench_thinvec_from_iter_and_drop_huge_dyn Instructions: 11953 L1 Accesses: 18323 L2 Accesses: 3 RAM Accesses: 62 Estimated Cycles: 20508 bench_std_vec_push_from_empty_few Instructions: 244 L1 Accesses: 346 L2 Accesses: 2 RAM Accesses: 7 Estimated Cycles: 601 bench_smallvec_push_from_empty_few Instructions: 19 L1 Accesses: 23 L2 Accesses: 2 RAM Accesses: 2 Estimated Cycles: 103 bench_wordvec_push_from_empty_few Instructions: 54 L1 Accesses: 71 L2 Accesses: 2 RAM Accesses: 7 Estimated Cycles: 326 bench_thinvec_push_from_empty_few Instructions: 252 L1 Accesses: 350 L2 Accesses: 2 RAM Accesses: 12 Estimated Cycles: 780 bench_std_vec_push_from_empty_small Instructions: 263 L1 Accesses: 378 L2 Accesses: 2 RAM Accesses: 11 Estimated Cycles: 773 bench_smallvec_push_from_empty_small Instructions: 23 L1 Accesses: 29 L2 Accesses: 2 RAM Accesses: 3 Estimated Cycles: 144 bench_wordvec_push_from_empty_small Instructions: 104 L1 Accesses: 144 L2 Accesses: 2 RAM Accesses: 8 Estimated Cycles: 434 bench_thinvec_push_from_empty_small Instructions: 277 L1 Accesses: 390 L2 Accesses: 2 RAM Accesses: 15 Estimated Cycles: 925 bench_std_vec_push_from_empty_large Instructions: 704 L1 Accesses: 996 L2 Accesses: 7 RAM Accesses: 24 Estimated Cycles: 1871 bench_smallvec_push_from_empty_large Instructions: 908 L1 Accesses: 1239 L2 Accesses: 9 RAM Accesses: 31 Estimated Cycles: 2369 bench_wordvec_push_from_empty_large Instructions: 939 L1 Accesses: 1326 L2 Accesses: 7 RAM Accesses: 18 Estimated Cycles: 1991 bench_thinvec_push_from_empty_large Instructions: 809 L1 Accesses: 1102 L2 Accesses: 8 RAM Accesses: 29 Estimated Cycles: 2157 bench_std_vec_push_from_empty_huge Instructions: 14747 L1 Accesses: 20732 L2 Accesses: 8 RAM Accesses: 58 Estimated Cycles: 22802 bench_smallvec_push_from_empty_huge Instructions: 20413 L1 Accesses: 27532 L2 Accesses: 10 RAM Accesses: 66 Estimated Cycles: 29892 bench_wordvec_push_from_empty_huge Instructions: 31983 L1 Accesses: 47051 L2 Accesses: 8 RAM Accesses: 60 Estimated Cycles: 49191 bench_thinvec_push_from_empty_huge Instructions: 14687 L1 Accesses: 20541 L2 Accesses: 8 RAM Accesses: 63 Estimated Cycles: 22786 bench_std_vec_push_from_empty_huge_dyn Instructions: 17108 L1 Accesses: 26283 L2 Accesses: 9 RAM Accesses: 62 Estimated Cycles: 28498 bench_smallvec_push_from_empty_huge_dyn Instructions: 22754 L1 Accesses: 34083 L2 Accesses: 11 RAM Accesses: 68 Estimated Cycles: 36518 bench_wordvec_push_from_empty_huge_dyn Instructions: 33311 L1 Accesses: 51563 L2 Accesses: 9 RAM Accesses: 62 Estimated Cycles: 53778 bench_thinvec_push_from_empty_huge_dyn Instructions: 17048 L1 Accesses: 26092 L2 Accesses: 8 RAM Accesses: 66 Estimated Cycles: 28442 bench_std_vec_remove_first_few Instructions: 181 L1 Accesses: 258 L2 Accesses: 2 RAM Accesses: 4 Estimated Cycles: 408 bench_smallvec_remove_first_few Instructions: 131 L1 Accesses: 162 L2 Accesses: 2 RAM Accesses: 14 Estimated Cycles: 662 bench_wordvec_remove_first_few Instructions: 115 L1 Accesses: 155 L2 Accesses: 2 RAM Accesses: 13 Estimated Cycles: 620 bench_thinvec_remove_first_few Instructions: 283 L1 Accesses: 392 L2 Accesses: 2 RAM Accesses: 15 Estimated Cycles: 927 bench_std_vec_remove_first_small Instructions: 184 L1 Accesses: 265 L2 Accesses: 2 RAM Accesses: 3 Estimated Cycles: 380 bench_smallvec_remove_first_small Instructions: 150 L1 Accesses: 188 L2 Accesses: 2 RAM Accesses: 13 Estimated Cycles: 653 bench_wordvec_remove_first_small Instructions: 201 L1 Accesses: 262 L2 Accesses: 2 RAM Accesses: 15 Estimated Cycles: 797 bench_thinvec_remove_first_small Instructions: 298 L1 Accesses: 417 L2 Accesses: 2 RAM Accesses: 16 Estimated Cycles: 987 bench_std_vec_remove_first_large Instructions: 193 L1 Accesses: 276 L2 Accesses: 2 RAM Accesses: 6 Estimated Cycles: 496 bench_smallvec_remove_first_large Instructions: 492 L1 Accesses: 635 L2 Accesses: 3 RAM Accesses: 21 Estimated Cycles: 1385 bench_wordvec_remove_first_large Instructions: 605 L1 Accesses: 782 L2 Accesses: 2 RAM Accesses: 20 Estimated Cycles: 1492 bench_thinvec_remove_first_large Instructions: 511 L1 Accesses: 696 L2 Accesses: 2 RAM Accesses: 25 Estimated Cycles: 1581 bench_std_vec_remove_first_huge Instructions: 1113 L1 Accesses: 1488 L2 Accesses: 4 RAM Accesses: 60 Estimated Cycles: 3608 bench_smallvec_remove_first_huge Instructions: 1383 L1 Accesses: 1798 L2 Accesses: 5 RAM Accesses: 77 Estimated Cycles: 4518 bench_wordvec_remove_first_huge Instructions: 1361 L1 Accesses: 1778 L2 Accesses: 4 RAM Accesses: 72 Estimated Cycles: 4318 bench_thinvec_remove_first_huge Instructions: 9977 L1 Accesses: 13330 L2 Accesses: 4 RAM Accesses: 65 Estimated Cycles: 15625 bench_std_vec_remove_second_small Instructions: 182 L1 Accesses: 260 L2 Accesses: 2 RAM Accesses: 4 Estimated Cycles: 410 bench_smallvec_remove_second_small Instructions: 154 L1 Accesses: 192 L2 Accesses: 2 RAM Accesses: 13 Estimated Cycles: 657 bench_wordvec_remove_second_small Instructions: 204 L1 Accesses: 265 L2 Accesses: 2 RAM Accesses: 15 Estimated Cycles: 800 bench_thinvec_remove_second_small Instructions: 301 L1 Accesses: 420 L2 Accesses: 2 RAM Accesses: 16 Estimated Cycles: 990 bench_std_vec_remove_second_large Instructions: 192 L1 Accesses: 275 L2 Accesses: 2 RAM Accesses: 5 Estimated Cycles: 460 bench_smallvec_remove_second_large Instructions: 493 L1 Accesses: 635 L2 Accesses: 3 RAM Accesses: 22 Estimated Cycles: 1420 bench_wordvec_remove_second_large Instructions: 604 L1 Accesses: 781 L2 Accesses: 2 RAM Accesses: 20 Estimated Cycles: 1491 bench_thinvec_remove_second_large Instructions: 511 L1 Accesses: 696 L2 Accesses: 2 RAM Accesses: 25 Estimated Cycles: 1581 bench_std_vec_remove_second_huge Instructions: 1113 L1 Accesses: 1488 L2 Accesses: 4 RAM Accesses: 60 Estimated Cycles: 3608 bench_smallvec_remove_second_huge Instructions: 1384 L1 Accesses: 1799 L2 Accesses: 5 RAM Accesses: 77 Estimated Cycles: 4519 bench_wordvec_remove_second_huge Instructions: 1360 L1 Accesses: 1777 L2 Accesses: 4 RAM Accesses: 72 Estimated Cycles: 4317 bench_thinvec_remove_second_huge Instructions: 9977 L1 Accesses: 13331 L2 Accesses: 4 RAM Accesses: 64 Estimated Cycles: 15591 bench_std_vec_inc_many_flat_empty Instructions: 24505 L1 Accesses: 31251 L2 Accesses: 54 RAM Accesses: 404 Estimated Cycles: 45661 bench_smallvec_inc_many_flat_empty Instructions: 52548 L1 Accesses: 69317 L2 Accesses: 54 RAM Accesses: 413 Estimated Cycles: 84042 bench_wordvec_inc_many_flat_empty Instructions: 60514 L1 Accesses: 88555 L2 Accesses: 12 RAM Accesses: 159 Estimated Cycles: 94180 bench_thinvec_inc_many_flat_empty Instructions: 26546 L1 Accesses: 36611 L2 Accesses: 14 RAM Accesses: 160 Estimated Cycles: 42281 bench_std_vec_inc_many_flat_small Instructions: 390210 L1 Accesses: 510587 L2 Accesses: 1859 RAM Accesses: 903 Estimated Cycles: 551487 bench_smallvec_inc_many_flat_small Instructions: 100548 L1 Accesses: 123317 L2 Accesses: 54 RAM Accesses: 413 Estimated Cycles: 138042 bench_wordvec_inc_many_flat_small Instructions: 98514 L1 Accesses: 135554 L2 Accesses: 12 RAM Accesses: 160 Estimated Cycles: 141214 bench_thinvec_inc_many_flat_small Instructions: 468248 L1 Accesses: 624396 L2 Accesses: 1361 RAM Accesses: 665 Estimated Cycles: 654476 bench_std_vec_inc_many_flat_large Instructions: 479041 L1 Accesses: 611621 L2 Accesses: 2359 RAM Accesses: 1160 Estimated Cycles: 664016 bench_smallvec_inc_many_flat_large Instructions: 644084 L1 Accesses: 822682 L2 Accesses: 2364 RAM Accesses: 1169 Estimated Cycles: 875417 bench_wordvec_inc_many_flat_large Instructions: 538340 L1 Accesses: 698993 L2 Accesses: 2359 RAM Accesses: 1169 Estimated Cycles: 751703 bench_thinvec_inc_many_flat_large Instructions: 602372 L1 Accesses: 795052 L2 Accesses: 2361 RAM Accesses: 1167 Estimated Cycles: 847702 bench_std_vec_inc_many_flat_huge Instructions: 4037660 L1 Accesses: 4535907 L2 Accesses: 34220 RAM Accesses: 32672 Estimated Cycles: 5850527 bench_smallvec_inc_many_flat_huge Instructions: 1924160 L1 Accesses: 2461663 L2 Accesses: 34993 RAM Accesses: 33684 Estimated Cycles: 3815568 bench_wordvec_inc_many_flat_huge Instructions: 3988669 L1 Accesses: 4899167 L2 Accesses: 33969 RAM Accesses: 32680 Estimated Cycles: 6212812 bench_thinvec_inc_many_flat_huge Instructions: 11390701 L1 Accesses: 14864226 L2 Accesses: 33973 RAM Accesses: 32676 Estimated Cycles: 16177751 bench_std_vec_inc_many_flat_pattern_all_small Instructions: 1404729 L1 Accesses: 1904822 L2 Accesses: 8242 RAM Accesses: 3121 Estimated Cycles: 2055267 bench_smallvec_inc_many_flat_pattern_all_small Instructions: 591450 L1 Accesses: 802969 L2 Accesses: 3114 RAM Accesses: 1561 Estimated Cycles: 873174 bench_wordvec_inc_many_flat_pattern_all_small Instructions: 387483 L1 Accesses: 545983 L2 Accesses: 149 RAM Accesses: 563 Estimated Cycles: 566433 bench_thinvec_inc_many_flat_pattern_all_small Instructions: 1556359 L1 Accesses: 2163215 L2 Accesses: 4454 RAM Accesses: 2117 Estimated Cycles: 2259580 bench_std_vec_inc_many_flat_pattern_mixed Instructions: 5265353 L1 Accesses: 6294018 L2 Accesses: 46083 RAM Accesses: 35130 Estimated Cycles: 7753983 bench_smallvec_inc_many_flat_pattern_mixed Instructions: 5404177 L1 Accesses: 6923460 L2 Accesses: 42143 RAM Accesses: 36228 Estimated Cycles: 8402155 bench_wordvec_inc_many_flat_pattern_mixed Instructions: 4849424 L1 Accesses: 6092814 L2 Accesses: 39749 RAM Accesses: 34141 Estimated Cycles: 7486494 bench_thinvec_inc_many_flat_pattern_mixed Instructions: 12808542 L1 Accesses: 16832469 L2 Accesses: 44128 RAM Accesses: 34630 Estimated Cycles: 18265159